The present invention concerns field-effect transistors, respectively a junction field-effect transistor and a metal-oxide semiconductor field-effect transistor (MOSFET) with substantially vertical geometry, wherein the field-effect transistors comprise a planar substrate, of non-conductive material. The invention also concerns a method for fabrication of field-effect transistors of this kind with a substantially vertical geometry, wherein the transistor comprises a planar substrate of non-conducting material.
Field-effect transistors (FET) which use an amorphous material as the active semiconductor are traditionally realized in a horizontal geometry such as rendered in FIG. 1 which shows two examples (FIG. 1a, FIG. 1b) of the realization of a thin-film field-effect transistor according to prior art. Here the drain electrode and the source electrode are mutually separated by a transistor channel. This channel consists of an amorphous semiconductor material. The gate electrode is defined as a horizontal layer which is isolated from the channel by means of the gate isolator. The transistor effect is defined either as a depletion mode or an enrichment mode, depending on the gate potential. As the active amorphous semiconductor material in field-effect transistors of this kind conjugated polymers, aromatic molecules, and amorphous inorganic semiconductors have been used. For instance FIG. 1 shows a thin-film transistor with an active semiconductor material in the form of amorphous Si:H in a 10 nm thick layer (D. B. Thomasson and al., IEEE El. Dev. Lett.,Vol. 18. p. 117; March 1997). A gate electrode which may be of metal, is provided on a substrate. An isolating layer of silicon nitride (SiN) is provided over this gate electrode and the active semiconductor material in form of amorphous Si:H is provided over the isolator in a 10 nm thick layer. The drain electrode and the source electrode are provided mutually spaced apart on the active semiconductor material. They are realized in a different metal than the gate electrode, for instance aluminum. Another example of an organic thin film transistor is shown in FIG. 1b (A. Dodabalapur and al., Appl. Phys. Lett.: Vol. 69, pp.4227-29, December 1996). Here the active semiconductor material is an organic compound, for instance a polymer or aromatic molecules. As in the example in FIG. 1a the gate electrode is provided on a substrate and above the gate electrode an isolator is provided in the form of a layer which may be made by coating the surface of the gate electrode with an oxide layer, something which may be realized by oxidizing the material in the surface of the gate electrode. The source and drain electrode are provided spaced apart on the isolating layer and spaced apart vertical side walls which on one end are mutually connected with a similar vertical transverse wall are provided over the drain and source electrode. In the plane perpendicular to the walls the transistor channel hence obtains a section formed as a U, where the side walls are the legs of the U and the transverse wall the crossline. The layers may be provided standing on a suitable substrate and wholly covered by a layer of isolating material. Over the isolating layer a conducting layer is provided, forming the gate electrode of the transistor. The ends of the side walls or the ends of the legs of the U shaped channel structure are exposed and in these end areas of the channel the source and drain electrodes respectively are formed, for instance by an ion implantation process. The primary object of a thin-film transistor of this kind is to provide a satisfying channel length on a smaller area than can be obtained with more conventional embodiments, while the stray current is reduced when the transistor is in an off-state.
FIG. 1c shows a schematically and in principle a planar JFET structure according to prior art, in this case realized as an n-channel JFET.
The use of an amorphous semiconductor material makes possible the realization of different transistor geometries if the very special processing properties of the amorphous materials are exploited. The object of the present invention is hence to provide a field-effect transistor, respective a junction field-effect transistor (JFET) and a metal-oxide field-effect transistor (MOSFET) with vertical geometry and even more particular the object is to deposit the amorphous active semiconductor material in the form of organic molecules, a conjugated polymer or an amorphous inorganic semiconductor on a vertical structure which comprises both the gate electrode and either the drain electrode or the source electrode. Finally it is also an object to provide a vertically oriented transistor channel.
Common semiconductor devices have formerly been made with vertical geometry. The purpose of this is a more effective exploitation of the chip area. A transistor with vertical geometry is expected to require less space than a transistor with horizontal geometry.
For instance it is from U.S. Pat. No. 5,563,077 (H.C. Ha) known a thin-film transistor with a vertical channel, wherein the channel is formed with two mutually spaced apart vertical side walls which at one end are connected with a similarly vertical end-wall. In the plane perpendicular to the walls the transistor channel hence obtains a U-shaped section, wherein the side walls are the legs of the U and the end wall the cross line. The walls may be provided on a suitable substrate and wholly covered by a layer of isolating material. A conducting layer which forms the gate electrode of the transistor is provided over the isolating layer. The ends of the side walls or the end of the U-shaped channel structure is exposed and on these end areas of the channel the source and drain electrodes respectively are formed, e.g. by means of an ion implantation process. The primary object of a thin film transistor of this kind is to provide a satisfying channel length on a smaller area than that which may be obtained with more conventional embodiments, while the leakage current is reduced when the transistor is in off-state.
The above-mentioned objects and other advantages are achieved according to the invention with a junction field-effect transistor (JFET) which is characterized in that a layer of conducting material which comprises a first electrode is provided on the substrate that a layer of isolating material which forms a first isolator is provided over the first electrode that a layer of conducting material which forms a second electrode is provided over the first isolator, that a further layer of isolating material which forms a second isolator is provided over the second electrode, that a layer of conducting material which forms a third electrode is provided over the second isolator, said first and third electrode respectively comprising the drain and source electrode of the transistor or vice versa and said second electrode the gate electrode of the transistor, that at least said second and said third electrode and said first and second isolator with the respective layers in stacked configuration form a step oriented vertically relative to said first electrode and/or said substrate, and that a semiconductor material which forms the active semiconductor of the transistor is provided over the exposed portion of said first electrode, said second electrode and said third electrode, said active semiconductor contacting the gate electrode directly and forming a substantially vertically oriented transistor channel between said first and said third electrode and a metal-oxide semiconductor field-effect transistor (MOSFET) which is characterized in that a layer of conducting material which comprises a first electrode is provided on the substrate, that a layer of isolating material which forms a first isolator is provided over the first electrode, that a layer of conducting material which forms a second electrode is provided over the first isolator, that a further layer of isolating material which forms a second isolator is provided over the second electrode, that a layer of conducting material which forms a third electrode is provided over the second isolator, said first and third electrode respectively comprising the drain and source electrode of the transistor or vice versa and said second electrode the gate electrode of the transistor, that at least said second and said third electrode and said first and second isolator with the respective layers in stacked configuration form a step oriented vertically relative to said first electrode and/or said substrate, that a vertically oriented layer of isolating material which forms a gate isolator is provided over said second electrode and on said vertical step, and that a semiconductor material which realizes the active semiconductor of the transistor and forms a substantial vertically oriented transistor channel between said first and said third electrode is provided over the exposed portion of said first electrode, said vertical step with said gate isolator and said third electrode.
Further the above-mentioned objects and advantages according to the invention are achieved with a method for fabrication of a field-effect transistor, characterized by the method comprising steps for depositing on said substrate a layer of conducting material which forms a first electrode, forming on the first electrode a step consisting of a photoresist and vertical relative to said first electrode and/or said substrate by means of a photolithograpic process, depositing respectively over both said conducting layer and said photoresist which form the vertical step, a first isolator, a conducting material which forms a second electrode, a second isolator and a conducting material which forms a third electrode in a layerwise stacked configuration, removing said configuration stacked over said photoresist and the photoresist itself by means of a lift-off method, whereby the remaining isolator-electrode configuration provided on the first electrode forms a step oriented vertically relative to said first electrode and/or said substrate, and depositing a soluble amorphous active semiconductor material over said first electrode, and said vertical step, such that semiconductor material contacts both said first and said third electrode which realize respectively a drain or source electrode and vice versa in a field-effect transistor, and said second electrode which realizes the gate electrode of the field effect transistor, thus forming a vertically oriented transistor channel.
Where the field-effect transistor is a metal-oxide field-effect transistor (MOSFET) it is advantageous that an isolating material is being deposited on the vertical step in a vertically oriented layer, which is provided over the second electrode and forms the gate isolator in a field-effect transistor, the deposition taking place after the removal of said stacked configuration and said photoresist, but before the deposition of the soluble amorphous active semiconductor material.
It is according to the invention also advantageous that the active semiconductor material is an amorphous inorganic or organic semiconductor material, but need not be restricted to amorphous semiconductor materials, as it may also be selected among polycrystalline or microcrystalline inorganic or organic semiconductor materials.
Further features and advantages are apparent from the remaining appended dependent claims.